Computer architecture : a quantitative approach

About the Authors......Page 5
Title page......Page 6
Copyright page......Page 7
Foreword......Page 10
Table of Contents......Page 12
This Edition......Page 16
An Overview of the Content......Page 19
Case Studies with Exercises......Page 21
Supplemental Materials......Page 22
Concluding Remarks......Page 23
Contributors to the Fourth Edition......Page 24
Contributors to Previous Editions......Page 26
1 Fundamentals of Computer Design......Page 30
1.1 Introduction......Page 31
1.2 Classes of Computers......Page 33
1.3 Defining Computer Architecture......Page 37
1.4 Trends in Technology......Page 43
1.5 Trends in Power in Integrated Circuits......Page 46
1.6 Trends in Cost......Page 48
1.7 Dependability......Page 54
1.8 Measuring, Reporting, and Summarizing Performance......Page 57
1.9 Quantitative Principles of Computer Design......Page 66
1.10 Putting It All Together: Performance and Price-Performance......Page 73
1.11 Fallacies and Pitfalls......Page 77
1.12 Concluding Remarks......Page 81
1.13 Historical Perspectives and References......Page 83
Case Studies with Exercises by Diana Franklin......Page 84
2 Instruction-Level Parallelism and Its Exploitation......Page 94
2.1 Instruction-Level Parallelism: Concepts and Challenges......Page 95
2.2 Basic Compiler Techniques for Exposing ILP......Page 103
2.3 Reducing Branch Costs with Prediction......Page 109
2.4 Overcoming Data Hazards with Dynamic Scheduling......Page 118
2.5 Dynamic Scheduling: Examples and the Algorithm......Page 126
2.6 Hardware-Based Speculation......Page 133
2.7 Exploiting ILP Using Multiple Issue and Static Scheduling......Page 143
2.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation......Page 147
2.9 Advanced Techniques for Instruction Delivery and Speculation......Page 150
2.10 Putting It All Together: The Intel Pentium 4......Page 160
2.11 Fallacies and Pitfalls......Page 167
2.12 Concluding Remarks......Page 169
2.13 Historical Perspective and References......Page 170
Case Studies with Exercises by Robert P. Colwell......Page 171
3 Limits on Instruction-Level Parallelism......Page 182
3.2 Studies of the Limitations of ILP......Page 183
3.3 Limitations on ILP for Realizable Processors......Page 194
3.4 Crosscutting Issues: Hardware versus Software Speculation......Page 199
3.5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism......Page 201
3.6 Putting It All Together: Performance and Efficiency in Advanced Multiple-Issue Processors......Page 208
3.7 Fallacies and Pitfalls......Page 212
3.8 Concluding Remarks......Page 213
Case Study with Exercises by Wen-mei W. Hwu and John W. Sias......Page 214
4 Multiprocessors and Thread-Level Parallelism......Page 224
4.1 Introduction......Page 225
4.2 Symmetric Shared-Memory Architectures......Page 234
4.3 Performance of Symmetric Shared-Memory Multiprocessors......Page 247
4.4 Distributed Shared Memory and Directory-Based Coherence......Page 259
4.5 Synchronization: The Basics......Page 266
4.6 Models of Memory Consistency: An Introduction......Page 272
4.7 Crosscutting Issues......Page 275
4.8 Putting It All Together: The Sun T1 Multiprocessor......Page 278
4.9 Fallacies and Pitfalls......Page 286
4.10 Concluding Remarks......Page 291
Case Studies with Exercises by David A. Wood......Page 293
5 Memory Hierarchy Design......Page 316
5.1 Introduction......Page 317
5.2 Eleven Advanced Optimizations of Cache Performance......Page 322
5.3 Memory Technology and Optimizations......Page 339
5.4 Protection: Virtual Memory and Virtual Machines......Page 344
5.5 Crosscutting Issues: The Design of Memory Hierarchies......Page 353
5.6 Putting It All Together: AMD Opteron Memory Hierarchy......Page 355
5.7 Fallacies and Pitfalls......Page 364
5.8 Concluding Remarks......Page 370
Case Studies with Exercises by Norman P. Jouppi......Page 371
6 Storage Systems......Page 386
6.2 Advanced Topics in Disk Storage......Page 387
6.3 Definition and Examples of Real Faults and Failures......Page 395
6.4 I/O Performance, Reliability Measures, and Benchmarks......Page 400
6.5 A Little Queuing Theory......Page 408
6.6 Crosscutting Issues......Page 419
6.7 Designing and Evaluating an I/O System - The Internet Archive Cluster......Page 421
6.8 Putting It All Together: NetApp FAS6000 Filer......Page 426
6.9 Fallacies and Pitfalls......Page 428
6.10 Concluding Remarks......Page 432
Case Studies with Exercises by Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau......Page 433
A Pipelining: Basic and Intermediate Concepts......Page 454
A.1 Introduction......Page 455
A.2 The Major Hurdle of Pipelining - Pipeline Hazards......Page 464
A.3 How Is Pipelining Implemented?......Page 479
A.4 What Makes Pipelining Hard to Implement?......Page 490
A.5 Extending the MIPS Pipeline to Handle Multicycle Operations......Page 500
A.6 Putting It All Together: The MIPS R4000 Pipeline......Page 509
A.7 Crosscutting Issues......Page 518
A.8 Fallacies and Pitfalls......Page 528
A.9 Concluding Remarks......Page 529
A.10 Historical Perspective and References......Page 530
B Instruction Set Principles and Examples......Page 532
B.1 Introduction......Page 533
B.2 Classifying Instruction Set Architectures......Page 534
B.3 Memory Addressing......Page 538
B.4 Type and Size of Operands......Page 544
B.5 Operations in the Instruction Set......Page 545
B.6 Instructions for Control Flow......Page 547
B.7 Encoding an Instruction Set......Page 552
B.8 Crosscutting Issues: The Role of Compilers......Page 555
B.9 Putting It All Together: The MIPS Architecture......Page 563
B.10 Fallacies and Pitfalls......Page 570
B.11 Concluding Remarks......Page 576
B.12 Historical Perspective and References......Page 578
C Review of Memory Hierarchy......Page 580
C.1 Introduction......Page 581
C.2 Cache Performance......Page 594
C.3 Six Basic Cache Optimizations......Page 601
C.4 Virtual Memory......Page 617
C.5 Protection and Examples of Virtual Memory......Page 626
C.6 Fallacies and Pitfalls......Page 635
C.7 Concluding Remarks......Page 636
C.8 Historical Perspective and References......Page 637
References......Page 638
Index......Page 666
About the CD......Page 705