Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and Electro-Magnetic Disturbances

5.2.3 Safety......Page 5
Preface......Page 6
 Reference......Page 7
  2.3.3 SEE Classification Techniques in Time Domain......Page 9
   2.4.1.3 Influence of Tap Locations......Page 13
  5.6.1 Autonomous Decentralized Systems......Page 21
  5.6.4 Ultra-Safe System......Page 23
Cover......Page 1
  5.2.2 Availability......Page 3
 References......Page 2
   4.2.1.4 Jitter in Single-Ended Signaling......Page 4
Contents......Page 10
 5.5 Technical Issues......Page 11
  5.5.1 High Performance......Page 12
List of Figures......Page 14
  5.5.4 Fault Tolerance of Fault Tolerance for Ultimate Safety......Page 15
   4.3.2.3 Target Impedance......Page 17
  5.5.5 Reliability of Software......Page 18
  2.5.4 SRAM Device Model......Page 20
List of Tables......Page 22
List of Acronyms......Page 24
   5.8.3.1 Fault-Injection Experiments......Page 28
 1.2 Contents and Organization of This Book......Page 29
   4.4.1.6 BGA......Page 30
   2.6.2.7 Trends in MCU Multiplicity Distribution......Page 32
  2.1.1 SER in Memory Devices......Page 33
  2.1.2 MCU in Memory Devices......Page 34
  2.2.1 Cosmic Rays from the Outer Space......Page 36
  2.2.2 Nuclear Spallation Reaction and Charge Collection in CMOSFET Device......Page 37
  2.3.1 The System to Quantify SER -- SECIS......Page 38
   2.3.2.2 (Quasi-)Mono-Energetic Neutron Test......Page 39
  2.3.3 SEE Classification Techniques in Time Domain......Page 41
   2.4.1.1 DUTs and Neutron Beams......Page 43
   2.4.1.2 MCU Patterns......Page 44
   2.4.1.3 Influence of Tap Locations......Page 45
   2.4.1.4 MCU Category......Page 46
  2.5.2 Nuclear Spallation Reaction Models......Page 50
 References......Page 51
  2.5.5 Cell Matrix Model......Page 53
   4.3.2.2 Frequency-Domain Analysis......Page 16
Acknowledgements......Page 8
 4.4 Modeling and Design Methodologies of PDS......Page 25
   4.4.1.1 Voltage Regulator Module (VRM)......Page 26
 1.3 For the Best Result......Page 31
  2.1.5 Scope of This Chapter......Page 35
  2.3.4 MCU Classification Techniques in Topological Space Domain......Page 42
  2.4.2 Multi-coupled Bipolar Interaction (MCBI)......Page 47
   4.6.2.2 Impulse Response Method......Page 48
 5.6 Industrial Approach......Page 19
 1.1 Trends in Failure Cause and Countermeasure......Page 27
  2.5.1 Overall Microscopic Soft-Error Model......Page 49
  2.5.6 Recycle Simulation Method......Page 54
   2.6.2.1 Overall Trends......Page 56
  2.5.4 SRAM Device Model......Page 52
  2.5.7 Validation of SRAM Model......Page 55
   2.6.2.2 Charge Deposition Density for Secondary Ions......Page 60
   2.6.2.3 Total Charge Collected to Storage Node......Page 61
   2.6.2.4 Failed Bit Map (FBM)......Page 62
   2.6.2.6 Trends in MCU Ratio......Page 64
  2.6.3 Validity of Simulated Results......Page 65
  2.7.2 Revisions Needed for the Standards......Page 66
  2.7.3 Quantification of SER in Logic Devices and Related Issues......Page 68
   2.8.1.1 Full and Partial Board Irradiation Test......Page 69
   2.8.1.2 Neutron Facility......Page 70
   2.8.1.3 Architecture of Test Component......Page 71
   2.8.1.4 Test Procedures......Page 73
   2.8.2.1 Test Results......Page 75
   2.8.2.3 Correlation Between the Irradiation Test and Field Data......Page 76
  2.9.1 Basic Three Approaches......Page 77
  2.9.2 Design on the Upper Bound (DOUB)......Page 78
 2.10 Inter Layer Built-In Reliability (LABIR)......Page 82
 2.11 Summary......Page 83
 References......Page 85
 3.1 Introduction......Page 90
  3.2.2 Calculation of the Electric Current Distribution on the Circuit Board......Page 93
  3.2.3 Calculation of the Far-Field Radiated EMI......Page 95
   3.3.1.2 Conventional and Proposed Technique for Obtaining Current Distribution......Page 96
   3.3.1.3 High-Resolution Current Detecting Technique......Page 99
  3.4.1 Far-Field Measurement of Chassis with PCB......Page 100
  3.4.2 Measurements of Junction Current......Page 104
  3.4.3 PSPICE Modeling......Page 105
  3.4.4 Experimental Validation......Page 110
 3.5 Chapter Summary......Page 111
 References......Page 113
 4.1 Introduction......Page 115
   4.2.1.1 Noise Margin Degradation......Page 116
   4.2.1.2 On-Chip Clock Timing......Page 117
   4.2.1.3 Signal Timing Uncertainty......Page 118
   4.2.1.5 Jitter in Differential Signaling......Page 120
  4.2.2 Trends of Power Supply Voltage and Power Supply Current for CMOS Semiconducting Devices......Page 122
  4.2.3 Trend of Power Distribution Network Design for Electronic Systems......Page 124
  4.3.1 Definition of Power Supply Noise in Electric System......Page 126
  4.3.2 Time-Domain and Frequency-Domain Design Methodology......Page 128
   4.3.2.1 Time-Domain (TD) Analysis......Page 129
   4.3.2.2 Frequency-Domain Analysis......Page 130
   4.3.2.3 Target Impedance......Page 131
   4.3.2.4 Comparison Between TD and FD Analyses......Page 138
 4.4 Modeling and Design Methodologies of PDS......Page 139
   4.4.1.1 Voltage Regulator Module (VRM)......Page 140
   4.4.1.2 Bypass Capacitor......Page 142
   4.4.1.3 Land of Bypass Capacitor......Page 143
   4.4.1.4 Power and Ground Planes......Page 144
   4.4.1.7 On-Chip Bypass Capacitors......Page 145
   4.4.2.1 Usage of Different Capacitors......Page 147
   4.4.2.3 Usage of a Large ESR......Page 148
  4.4.2.5 Place Components as Close as Possible......Page 149
  4.5.1 Principle of SSN......Page 150
  4.5.2 S--G loop SSN......Page 151
  4.5.3 P--G loop SSN......Page 153
   4.6.1.1 DAC......Page 155
   4.6.1.2 Ring Oscillator......Page 156
   4.6.1.3 Delay Observation......Page 159
   4.6.2.1 Integrated Power Supply Frequency Domain Impedance Meter (IFDIM)......Page 161
   4.6.2.2 Impulse Response Method......Page 162
 4.7 Summary......Page 164
 References......Page 165
 5.1 Introduction......Page 167
  5.2.1 Reliability......Page 168
  5.2.2 Availability......Page 169
  5.2.3 Safety......Page 171
 5.3 Reliability Paradox......Page 172
 5.4 Survey on Fault-Tolerant Systems......Page 174
 5.5 Technical Issues......Page 177
  5.5.1 High Performance......Page 178
  5.5.2 Transparency......Page 180
  5.5.4 Fault Tolerance of Fault Tolerance for Ultimate Safety......Page 181
  5.5.5 Reliability of Software......Page 184
 5.6 Industrial Approach......Page 185
  5.6.1 Autonomous Decentralized Systems......Page 187
  5.6.3 Commercial Fault-Tolerant Systems......Page 188
  5.6.4 Ultra-Safe System......Page 189
  5.8.1 Basic Concept......Page 190
  5.8.2 Hiten Onboard Computer......Page 193
   5.8.3.1 Fault-Injection Experiments......Page 194
   5.8.3.2 Field Data......Page 195
  5.8.4 Extension of SNV -- Redundancy Management......Page 197
 5.9 Coverage Improvement......Page 199
  5.9.1 Self-Checking Comparator......Page 200
  5.9.2 Optimal Time Diversity......Page 203
 5.10 On-Chip Redundancy......Page 208
   5.11.1.1 System Reconfiguration by Collaboration of Hardware and Software......Page 212
   5.11.1.2 Intra-board Fault-Masking......Page 213
  5.11.4 Processing Take-Over on Fault Occurrence......Page 215
   5.11.5.1 Fault Tolerance of System Reconfiguration......Page 216
  5.11.6 Commercial Product Model......Page 219
 5.12 Current Application Field: X-by-Wire......Page 220
 References......Page 222
6 Challenges in the Future......Page 225
 References......Page 226
Index......Page 227