High Dielectric Constant Materials: VLSI MOSFET Applications

Contents......Page 9
1.2 Moore\'s Law: A Description......Page 24
1.3 The History of Moore\'s Law......Page 25
1.4 The Microeconomics of Moore\'s Law......Page 36
1.5 The Macroeconomics of Moore\'s Law......Page 44
1.6 Moore\'s Law Meets Moore\'s Wall: What is Likely to Happen......Page 46
1.7 Conclusion......Page 50
1.8 Appendix A......Page 51
References......Page 53
Part I Classical Regime for SiO[sub(2)]......Page 54
2.1 Early Attempts to Make Insulating-Gate Field-Effect Transistors; Surface States......Page 55
2.2 Passivation of Silicon Surfaces by Thermal Oxidation; Planar Transistor Technology......Page 56
2.3 Positive Oxide Charge and Surface States at the Si–SiO[sub(2)] Interface......Page 57
2.4 Instabilities Due to Ion Drift Effects......Page 58
2.6 Other Materials Tried as Gate-Dielectric Layers......Page 59
2.7 Thermal Oxidation of Silicon......Page 60
2.8 Segregation of Dopants at the Si–SiO[sub(2)] Interface......Page 61
2.9 Other Silicon Oxide Preparation Techniques......Page 62
2.12 Weak Oxide Regions in MOS Structures Kooi Effect......Page 63
2.14 Silicon Gate MOS Devices, NMOS and CMOS IC\'s......Page 64
References......Page 65
3.1 SiO[sub(2)] Prior to 1970......Page 67
3.2 After 1970: Progress in Understanding......Page 77
3.3 Modern Era: The Quest for Thinner SiO[sub(2)] and Alternatives......Page 98
References......Page 108
4.1 Thin Oxide Layer Degradation Under Electrical Stress......Page 113
4.2 Oxide Breakdown......Page 124
4.3 Breakdown Acceleration Models......Page 129
References......Page 133
Part II Transition to Silicon Oxynitrides......Page 143
5.1 Device Requirements on Gate Dielectric Scaling......Page 144
5.2 Definition of Gate Dielectric Thickness......Page 148
5.3 Tunneling Current of SiO[sub(2)]......Page 153
5.4 Tunneling Currents of Silicon Oxynitride......Page 156
5.5 Application Dependence of Gate Dielectric Limit......Page 158
References......Page 161
6.1 Introduction......Page 164
6.2 Scaling and Device Physics......Page 166
6.3 Limitations of Conventional Scaling......Page 175
6.4 Extending Validity of Moore\'s Law......Page 186
6.5 Conclusions......Page 211
References......Page 213
7.1 Introduction......Page 216
7.2 Integrated RTCVD Oxynitride (ION) Process......Page 218
7.3 JVD Nitride......Page 228
7.4 DPN Oxynitride......Page 232
7.5 Conclusion......Page 239
References......Page 240
Part III Transition to High-k Gate Dielectrics......Page 242
8.1 Introduction......Page 243
8.2 Discussion......Page 246
8.3 Conclusions......Page 267
References......Page 268
9.1 Introduction......Page 272
9.2 MIS (Metal-Insulator-Semiconductor) Structures......Page 276
9.3 Materials Properties and Integration Considerations......Page 280
References......Page 296
10.1 Introduction......Page 306
10.2 Thermodynamic Stability of Dielectrics on Silicon......Page 309
10.3 Kinetic Rate Processes During Metal Oxide Deposition......Page 316
10.4 Gate Electrode/Dielectric Interfaces......Page 323
10.5 Conclusion......Page 324
References......Page 325
11.1 Introduction......Page 330
11.2 SiO[sub(2)] and the Si–SiO[sub(2)] Interface......Page 332
11.3 Alternative Dielectrics......Page 341
11.4 Electronic Structure of Transition Metal Dielectrics......Page 346
11.5 Experimental Studies of Electronic Structure......Page 352
11.6 Interface Electronic Structure Applied to Direct Tunneling in Silicate Alloys......Page 367
11.7 Conclusion......Page 372
References......Page 374
12.1 Introduction......Page 377
12.2 Crystal Lattice Site of 4d, 5d, and Rare Earth Metals in Silicon......Page 378
12.3 Solubility of 4d, 5d, and Rare Earth Metals in Silicon......Page 379
12.4 Diffusivity of 4d, 5d, and Rare Earth Elements in Silicon......Page 380
12.5 Energy Levels in the Band Gap......Page 386
12.6 Effect of 4d, 5d, and Rare Earth Metals on Minority Carrier Recombination Lifetime and Device Performance......Page 390
12.7 Summarizing Discussion......Page 392
References......Page 393
13 High-k Gate Dielectric Deposition Technologies......Page 397
13.1 Atomic Layer Deposition......Page 398
13.2 Chemical Vapor Deposition......Page 409
13.3 Plasma-Enhanced Atomic Layer Deposition......Page 411
13.4 Plasma Enhanced Chemical Vapor Deposition......Page 414
13.5 Physical Vapor Deposition......Page 417
13.6 Molecular Beam Epitaxy......Page 421
13.7 Ion Beam Assisted Deposition......Page 422
13.8 Sol-gel Deposition......Page 423
13.9 Summary......Page 424
References......Page 425
14.1 Background......Page 432
14.2 Metal Gate Selection Criteria......Page 433
14.3 Other Challenges with Metal Gates......Page 435
14.4 Metal Gate Candidates for NMOS Devices......Page 436
14.6 Metals on High-k Dielectrics......Page 447
14.7 Conclusion......Page 448
References......Page 449
15.1 Introduction......Page 452
15.2 The \"Standard\" CMOS Flow......Page 453
15.3 Insertion of High-k Gate Dielectric into the CMOS Flow......Page 459
15.4 Alternative Electrode Materials......Page 466
15.5 Integration of High-k Gate Dielectrics and Metal Gates into Advanced Devices......Page 478
15.6 Conclusions......Page 487
References......Page 488
16.1 Introduction......Page 499
16.2 Structural and Chemical Characterization of Medium ε Film Stacks......Page 502
16.3 Optical Models for Medium κ Films......Page 519
References......Page 533
17.1 Introduction......Page 537
17.2 Capacitance–Voltage Measurement......Page 538
17.3 Analysis of Device/Material Parameters from Established C–V Data......Page 564
17.4 Current-Voltage Measurement......Page 567
17.5 Determination of DC Conduction Mechanisms......Page 572
17.6 Sample Design and Preparation Issues......Page 576
References......Page 578
18.1 Introduction......Page 583
18.2 Fundamental Issues on Gate Capacitance and Current Modeling......Page 584
18.3 Wave Function Penetration Effect Issues......Page 595
18.4 Maxwell–Wagner Effects and Power Law Dispersion......Page 607
18.5 Conclusions......Page 618
References......Page 619
Part IV Future Directions for Ultimate Scaling Technology Generations......Page 621
19.1 Introduction......Page 622
19.2 The Path to the Perovskites and COS......Page 625
19.3 The Material System of COS......Page 629
19.4 The Implementation of COS......Page 634
19.5 Electrical Properties......Page 644
19.6 Conclusion......Page 649
References......Page 650
20.1 Introduction......Page 653
20.3 Perovskite Surface......Page 658
20.4 Oxide Deposition......Page 661
20.5 Growth Template......Page 662
20.6 Substrate Preparation......Page 663
20.7 Initial Nucleation......Page 664
20.8 Stability of the Interface......Page 667
20.9 Structural Properties......Page 668
20.10 Band Discontinuity......Page 672
20.11 Device Results......Page 675
20.12 Conclusion......Page 677
References......Page 678
21.1 Introduction......Page 681
21.2 The Ballistic Nanotransistor......Page 688
21.3 Vertical Replacement Gate MOSFET......Page 695
21.4 The Double-Gate FinFET......Page 702
21.5 Silicon-On-Nothing MOSFETs......Page 706
21.6 Conclusion......Page 715
References......Page 716
E......Page 720
M......Page 721
S......Page 722
X......Page 723